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double_fpu_verilog

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Please update latency numbers #2
Open jmcgttgl opened this issue over 4 years ago
jmcgttgl commented over 4 years ago

Latency seems to be larger than reported in the overview. Measuring from enable active on a rising clock edge to ready rising, I get the following with the non-pipelined version:

Add = 25 Sub = 26 Mul = 29 Div = 76

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