double_fpu_verilog

Incomplete flush of exception logic #3

Open jmcgttgl opened this issue over 5 years ago

There seems to be a bug in the exception logic during a multiply operation. An inexact condition from the previous operation can affect the value of out during the first cycle after ready asserts. Either the exception logic is incompletely flushed from the previous op, or the ready and out signals for the new operation are one cycle premature.