Logic correctly passes gray coded pointers between clock domains.
However, only one synchronizing register stage is used when two are necessary. This is covered quite well in literature, but basically the problem is this:
When a register samples a changing input signal, the result on the Q output of the FF is quite often neither '1' nor '0'. A certain amount of settling time is required before the FF goes to the correct value. This is called metastable recovery time. Any logic that follows must not be used before the recovery time has elapsed.
Left to it's own devices, synthesis can spend up to the entire clock period after the 1st FF converting gray code back into binary. That would leave no margin for metastable recovery. When a metastable event occurs, the delay can propagate through the gray2binary conversion, violating setup times on the next stage and causing an erroneous pointer to be used... exactly the condition we are trying to prevent!
A 2nd resynchronizing FF is required to provide an entire clock period of recovery time. The Q output is stable and can STATIC TIMING ANALYSIS.
Path delay between the 1st and 2nd resynchronizing flip flop should be minimized in order to provide the maximum amount of metastable recovery time. This is also synthesis issue, but much less of one.