in specification doc,
"According to IEEE802.3 ,The minimum IfG value is 96bit. If the system clock is 125Mhz with 8bit data width, the interval time between packet is at least 18 clock cycles"
is the '18 clock cycles' right? or d12 -> h12 -> d18 mistake?
Could you tell me where is IFG Value in the code files?
The default IFG is defined in reg_int.v and equals to h0c (so this is decimal 12 instead of hex 12!):
line 69: RegCPUData U_0_004(IFGset ,7'd004,16'h000c,Reset,Clk_reg,!WRB,CSB,CA,CD_in); line 90: RegCPUData U_0_025(RX_IFG_SET ,7'd025,16'h000c,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
Type your text here
I believe the spec is wrong, default is 12 clock cycles which makes sense since the standard interframe gap is 12 octets (or 96 bits)