Not sure whether this is a bug or not. (I'm using RGMII interface, when I convert RGMII to GMII following the standard before feeding GMII signals into phy_int) In phy_int, rx path, the error signal (MRxErr) goes through 1 stage of FF, whilst the Data valid signal (MCrs_dv) going through 3 stages of FFs. The symptom would be receiving a lot of Error for good packet if you plug the module into a normal network switch.
Type your text here
I can confirm that it is a bug, at least I tried for 1000Mbps. Users also reported that RX packets with an odd number of bytes get lost. I also noticed this behavior. When fixing this bug, also RX packets with odd number of bytes are received fine.
The right behavior can be easily checked with a testbench, where the RxErr = !RxDv. So the error signal is always '1' between frames. According to the 802.3 standard, this behavior is valid and some PHYs (at least my one as it seems) behave like this.