10_100_1000 Mbps tri-mode ethernet MAC

I used this core and experienced following two key point:

• first apply fix which is related state machine bug fix (stateIDLE2/stateIDLE3)

• initialize IFG times as 18 like stated in specification

then core did not work due to two problem :

First : gtx_clk pin needs to be driven by ODDR2 output register type due to become clocking output. When you use ODDR2 output register in tap module and direct it into the CORE it gives error again because this signal is used for some other inputs under clock control. Therefore; take ODDR2 into clk_ctrl and comment out Gtx_clk assignment and drive this pin from ODDR2 instance output.

Second: I saw whole signal correctly in test bench simulation results,however; i can not see the similar behavior when i load the design into fpga. So i focused on the difference and found out that i was applying reset signal to the core for particular time. When i remove reset signal from simulation the core could not drive tx_en tx_data pins of MII. So i applied some time of reset to the core then it worked.