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10_100_1000 Mbps tri-mode ethernet MAC

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Error with absence `timescale #30
Open Juzujka opened this issue about 1 year ago
Juzujka commented about 1 year ago

Modelsim 10.5b, from Intel (Altera) Quartus 17.1

** Error (suppressible): (vsim-3009) TSCALE - Module 'MAC_tx_addr_add' does not have a timeunit/timeprecision specification in effect, but other modules do.

Time: 0 ps Iteration: 0 Instance: /tb_top/U_MAC_top/U_MAC_tx/U_MAC_tx_addr_add File: ../../../../rtl/verilog/MAC_tx/MAC_tx_addr_add.v

Adding to MAC_tx_addr_add.v the line

`timescale 1 ns / 1 ns

solved this error.


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