10_100_1000 Mbps tri-mode ethernet MAC

In the file ./sim/rtl_sim/modsim_sim/bin/vlog-rtl.list ../../../../rtl/verilog/Reg_int.v should be spelled with lower case : reg_int.v

(Important when executing under case sensitive systems as UNIX/linux.)

(But then when trying to simulate, the modelsim pli files using .dll doen't really go well together with solaris;-)