Issue List
Combinational Timing loop #1
Open khusid opened this issue almost 21 years ago
khusid commented almost 21 years ago

After synthesizing your design with Synplify and Design Compiler, both tools reported of a combinational timing loop in post_norm stage. Although, they still synthesized the design, some advanced timing features in these tools refuse to deal with a timing loop (such as balance_register feature in Design Compiler). Timing loops in general is not a good idea, and if you ever plan on modifying your code, I would recommend removing the loop.

Also, overall, I'd like to see the code slightly better documented in the code itself, better pipelining (or rather more clear) and perhaps break up stages (such as post_norm) into smaller modules.

nirankul2003 commented over 8 years ago

I have an exact similar issue when synthesized using Cadence RTL Compiler.

jiang.long commented over 8 years ago

There is a combo loop involving :






in post_norm.v

Is this intentional? My tool can not process it due to the loop. Is there a way to get around it ?

No one