Floating Point Adder and Multiplier

I utilize your IP fpadd_pipeline with Quartus2- Altera. But it doesn't wotk well. I think fpadd_normalize_struct .vhd has a bug at the line 94 "IF (signed(count) > signed(EXP_in)) THEN". I think "singed" before "(count)" and "(Exp_in)" is not necessary. How do you think?

Type your text here

Same issue encountered: Add these two numbers with the last revision of fpadd_normalize_struct.vhd:

  a <= 32'hc5b3db3a;
  b <= 32'h451f0dd4;

I switched to previous one.

The hex operands are: c5b3db3a; 451f0dd4;

Lane IF (signed(count) > signed(EXP_in)) THEN

should be replaced with: IF ((count) > (EXP_in)) THEN

there is currently a bug related to the normalized numbers. It does work better with the previous version, I hope to have time in the next two weeks to finally close that issue (has been hanging for some time now...).

Granted, signed does not seems to be needed at this point. It will certainly assume the wrong sign from the count for some values, and when sign extending will return the wrong value. Will check it further. Thanks!

Can i get a Verilog code for master an slave of i2c in Verilog

Ashwini, I think you posted in the wrong place.

is this issue solved. if so i need it urgently