FT2232H USB Avalon Core

Hi,

your core works quite well. I just saw that you assert usb_wr_n only every 2nd cycle. This limits the performance to 30MBps which is quite good but I already saw 40MBps as possible maximum for a FT2232H.

For all others here are some resource figures for the core: FPGA: Cyclone III EP3C5F144C8 FTDI: FT2232H in synchronous FIFO mode TX+RX-Fifos: set to 1024 bytes

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Fitter Resource Utilization by Entity ; +------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+ ; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; +------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+ ... ; |usb_sync:inst_usb_sync| ; 355 (14) ; 270 (3) ; 0 (0) ; 16384 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 85 (10) ; 136 (0) ; 134 (4) ; ; |dcfifo:rx_dcfifo| ; 174 (0) ; 135 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 39 (0) ; 66 (0) ; 69 (0) ; ; |dcfifo:tx_dcfifo| ; 169 (0) ; 132 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 36 (0) ; 70 (0) ; 63 (0) ;

This bug can be fixed by changing the ft2232_wait signal from integer to std logic,

i.e:

ft2232_wait :std_logic := '0';

then change any assignments / checks to match the new type i.e set equal to '1' instead of incrementing by 1.