G.729A Codec

I need some inputs about you G729 codec which you shared in opencores.

When I add the files into Xilinx for simulation, I find the following VHDl modules to be missing in the filelist. Can you please provide the same: G729_ASIP_ROM_MIF G729_ASIP_ROM_MIF_2R G729_ASIP_IO_INTF G729_ASIP_ST_CHECKER G729_ASIP_WB_CHECKER

In the Readme file its mentioned that , we need to add G729A_asip_rom_1r.vhd G729A_codec_rom_st.vhd (Group5) for simulation with Self_test in Xilinx Platform. But these files are not available here.

Please help us with the same. Its urgent . While running simulation in ISIM , we are getting the following error:

at 27670 ns, Instance /g729a_codec_selftest_tb/U_DUT/U_CODEC/U_ASIP/g_romd_0/U_ROMD/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

at 27670 ns, Instance /g729a_codec_selftest_tb/U_DUT/U_CODEC/U_ASIP/U_RAMD/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

at 27670 ns(1), Instance /g729a_codec_selftest_tb/U_DUT/U_CODEC/U_ASIP/U_ASIP/U_BJXLOG/ : Warning: NUMERIC_STD."=": metavalue detected, returning FALSE

at 27670 ns(1), Instance /g729a_codec_selftest_tb/U_DUT/U_CODEC/U_ASIP/U_ASIP/U_PIPEB/U_MUL/ : Warning: NUMERIC_STD."=": metavalue detected, returning FALSE

at 27670 ns(3), Instance /g729a_codec_selftest_tb/U_DUT/U_CODEC/U_ASIP/U_ASIP/U_PIPEB/U_MUL/ : Warning: NUMERIC_STD.">": metavalue detected, returning FALSE

at 27670 ns(3), Instance /g729a_codec_selftest_tb/U_DUT/U_CODEC/U_ASIP/U_ASIP/U_PIPEB/U_MUL/ : Warning: NUMERIC_STD."<": metavalue detected, returning FALSE

at 27690 ns, Instance /g729a_codec_selftest_tb/U_DUT/U_CODEC/U_ASIP/g_romd_0/U_ROMD/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

at 27690 ns, Instance /g729a_codec_selftest_tb/U_DUT/U_CODEC/U_ASIP/U_RAMD/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

G729A_ASIP_ROM_MIF and G729A_ASIP_ROM_MIF_2R modules are specified by VHDL file G729A_asip_rom_mif.vhd, which is located in VHDL directory (see the script in SYN/ALTERA directory). These files are needed for synthesis on Altera FPGA only, and should NOT be used for behavioral simulation, or synthesis on Xilinx FPGA as explained by core documentation, page 6.

G729A_ASIP_IO_INTF module is permanently disabled by constant IO_INTF_PRESENT being hard-coded to '0' in file G729A_asip_top_2w.vhd. Please do not modify it!

G729A_ASIP_ST_CHECKER and G729A_ASIP_WB_CHECKER modules are disabled by core generic SIMULATION_ONLY which should be set to '0' as specified by core documentation, page 6.

G729A_asip_rom_1r.vhd is not needed, README.txt file in VHDL directory is incorrect about it.

The messages listed above are warning messages, not error ones.