HDB3/B3ZS Encoder+Decoder

Márcio Gama reported that the encoder core will produce an incorrect output for the first few clocks after reset if the data input is zero.

This is unlikely to cause problems in any practical application.

I'm not planning to fix this in the near future.

This isn't actually a bug. The encoder needs to look at the history of the input data signal. At the start of simulation, it takes a guess that the "preceding" bits were all 1. This seemed to be the right choice for an HDB3 encoder as E1 AIS is represented by all 1s. (N.B. the initial value of the history after reset doesn't make any difference to any practical application.)

The test bench included with the core ignores the output for a the first few clocks after reset and will work regardless of the initial value of the history.

If a user's test bench assumes that the history was all zero, then the encoder will appear to produce an incorrect output for the first few clocks after a reset.

BTW, I had left this bug report open for some years as (based on the emails I get) many downloads are from educational institutions and I wanted the students to try to actually understand the design.