I2C controller core

The Wishbone bus interface as implemented in the IIC module will capture write data twice because of the bus wait state introduced by the register generating the wb_ack signal. If the wb_cyc_i and wb_stb_i are valid before the first rising edge of the wb_clk_i in a bus transaction then a valid wb_wacc will be generated to allow the IIC control registers to capture the write data from the WISHBONE bus. Because the WISHBONE bus cycle is forced to be two cycles long wb_cyc_i and wb_stb_i will remain active for another wb_clk_i cycle allowing the IIC control registers to be written again on the second rising edge of wb_clk_i. This means that for correct bus operation all of the the signals, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i, and wb_dat_i must be valid on the same rising edge of wb_clk_i. If the designer allows wb_adr_i and wb_dat_i to be multi-cycle paths, because they are heavily loaded, durning synthesis the wrong data may be captured to the wrong register in the physical circuit. Consider the timing diagram below: At "IIC REGISTER CAPTURE POINT" "1" the data "D1" is captured in error to the register at address "A1" but because the address is allowed time to stabilize into the second clock cycle of the bus transaction a second correct capture of data "D2" at address "A2" occurs.

wb_clk_i _|''''''''''''''''''''|____|''''''''''''''''''''|____|''''''''''''''''''''|____| wb_cyc_i ____|'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''|___ wb_stb_i ____|'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''|___ wb_wacc _|''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''|__ wb_acc_o ___|'''''''''''''''''''''''''''''''''''''''''''''''''''|____ wb_adr_i AXAXAXAXAXAXAXAXAXA1A1A1A1A1A1A1A1A1A2A2A2A2A2A2AXAXAXAXAXAX wb_dat_i DXDXDXDXDXDXDXDXDXD1D1D1D1D1D1D1D1D1D2D2D2D2D2D2DXDXDXDXDXDX IIC REGISTER CAPTURE POINTS............1.................................2..................

There are two ways to handle this problem: 1) Over-constrain the timing so that all inputs are valid before the first wb_clk_i rising edge. This wastes the bus wait state forced by the wb_acc_o register and the correct data still gets latched to the correct address twice. If the single cycle timing constraint can be met then the wb_acc_o register could be removed and wb_acc_o could be generated combinationaly if it's single cycle timing constraint could also be met. 2) Add wb_acc_o from the register output as a qualifier to the signal wb_wacc. This gives the most timing latitude because the write data will only be latched in the final clock cycle when it is ack'ed with wb_acc_o.

Fixed ....

Fixed.

Richard

Fixed