Issue List
I2C core and Max Wishbone frequency #14
Closed gerry opened this issue almost 15 years ago
gerry commented almost 15 years ago

Im using the I2C core on a 100MHz Wishbone bus implemented on ALTERA cycloneII with Quartus 7.2 compiler and I observed a problema in SCL frequency output. The I2C slave here is a simple PCF8574 device.

I try to set 100KHz SLC clock and ss from your documentation I set:

prescale = 100MHz/(5*100KHz) -1 = 199 (dec) = C7 (hex)

The measured frequency of the scl on the oscilloscope is around 1.5KHz

There is any limit in the implementation related the Wishbone frequency I use that can explain the SCL behaviour ?


gerry commented almost 15 years ago

I got the problem in my wishbone implementation logic. Everything works fine with 100MHz clock now. I think you can close this one issue!

rherveille closed this almost 15 years ago

No one