Issue List
blocking and non-blocking #15
Closed markman opened this issue almost 15 years ago
markman commented almost 15 years ago

In i2c_master_bit_ctrl.v line 205 to line 207 always @(posedge clk or negedge nReset) if (!nReset) slave_wait <= 1'b0; else slave_wait = (scl_oen & ~dscl_oen & ~sSCL) | (slave_wait & ~sSCL);

mix with both blocking and non-blocking assignments to slave_wait, synthesis tool will give warnings. line 373 "case (c_state) " used the full_case synthesis attribute in a Case Statement that does not contain all possible state values or a Default Statement. The full_case synthesis attribute directs Analysis & Synthesis to treat unspecified state values in the Case Statement as Don't Care values. Analysis & Synthesis implemented the full_case synthesis attribute; however, in doing so, Analysis & Synthesis may have created synthesized logic for the current design with functionality that differs from the functionality when simulating for the design.

rherveille was assigned over 14 years ago
rherveille closed this over 14 years ago