I2C controller core

Hi Richard, I have implemented an I2C core with success on an Actel FPGA. Now I'm facing with a problem which arises when the I2C bus is heavy loaded with several devices and meters of cable. the master core, after putting the SDA line at logic 1, reads a 0 on the line itself, due to the slow SDA positive signal edge. This asserts an arbitration lost, which isn't the case. I see two possible solutions: 1) inhibit arbitration on I2C core (losing specs compliance) 2) delay sda_chk to case c_state wr_c only... what do you suggest? regards -Antonio-

The core reads (or at least it should) the line status in the middle of the clock. When the signal value is not settled yet then, you get into troubles.

First obvious questions; are you sure setup time is met? I.e. is the SDA signal correct (on time)?? A possible solution to your problem is to lower the bus speed. You are talking about meters of cable. I would try a very low bus speed first (e.g. 10kHz or even less).

Richard

at lower speeds all is working well (up to 50 kbps). to answer to your question, both SDA and SCL show similar delayed edges due to heavy capacitive load on the bus, so that setup seems to be met. You say "The core reads the line status in the middle of the clock", but SDA on the bus is delayed with respect to master clock, causing an undesired arbitration lost. I succeded in pushing up the rate beyond 400 kbps (this is the aim of my project) with the following tricks: 1) make SDA changes nearer falling edges of SCL 2) eliminate sda_chk when c_state=wr_c in i2c_master_bit_ctrl module ( I wonder if this puts out of I2C specs for arbitration) what do you think of these core changes?

maybe the April 30 2009 "extra SCL tick" bug has the same arbitration lost cause?

I delayed SDA checking until the WR_C state. That should allow sufficient time for SDA to settle.

Richard

I moved SDA checking to wr_c state, that should allow sufficient time for SDA to settle.

Richard