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Init filter_cnt #21
Closed jon_vdb opened this issue almost 14 years ago
jon_vdb commented almost 14 years ago

The filter_cnt code in i2c_master_bit_ctrl is different between the VHDL version and Verilog versions. In Verilog the counter is only started when ena = 1, in the VHDL version the counter starts after reset and one has to wait 0x4000 master clk cycles before I2C communication can begin correctly.

jon_vdb commented almost 14 years ago

Type your text here

rherveille was assigned almost 14 years ago
rherveille closed this almost 14 years ago
rherveille commented almost 14 years ago

Fixed in revision 76


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rherveille
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Bug