I2C controller core
Init filter_cnt #21
Closed jon_vdb opened this issue over 14 years ago
jon_vdb commented over 14 years ago
The filter_cnt code in i2c_master_bit_ctrl is different between the VHDL version and Verilog versions. In Verilog the counter is only started when ena = 1, in the VHDL version the counter starts after reset and one has to wait 0x4000 master clk cycles before I2C communication can begin correctly.
jon_vdb commented over 14 years ago
Type your text here
rherveille was assigned over 14 years ago
rherveille closed this over 14 years ago
rherveille commented over 14 years ago
Fixed in revision 76
© copyright 1999-2018 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.