I2C controller core

Using prescale formular ((sysclk/(5 x scl)))-1 with sysclk = 16000 (for 16Mhz) and scl = 100 (for 100kbit target i2c clock) generates 90kbit i2c clock instead of 100kbit.

By the way, the latest documentation v0.9 (in the trunk/doc folder)is dated from 2003, is that the latest? Rev. 0.3 March 6, 2001 Rev. 0.9 July 3, 2003 Might be there a new formular for calculating scl?

Lutz

?ause of this effect is slave_wait signal in i2c_master_bit_ctrl block. Though slave clock stretching is absent, slave_wait is active some periods of system clock.

?ause of this effect is slave_wait signal in i2c_master_bit_ctrl block. Though slave clock stretching is absent, slave_wait is active some periods of system clock.

Did you find a workaround for this? I have a similar but slightly weirder issue: with a 100MHz sysclk, in simulation I get a 90kbit clock just as you did; but with actual implementation I'm only getting a 58kbit clock. The device I'm talking to is an EEPROM rated to 400kbit, so I don't think it's doing any clock stretching.

I ran this in both the Xilinx simulator and in actual HW. It appears to wait for clock sync on every cycle. For me this adds approximately 27 extra dead clock cycles per I2C clock. If I account for this extra dead time when calculating the prescaler, then the clock rate is pretty good. My system clock is 33MHZ. Below is my C code calculation.

fModSMBUS_Period = (1.0f/nDesiredClkRate) - (27.5f/33000000.0f);
nPrescaler = (u_int32_t)(( 33000000.0f / (5.0f * (1/fModSMBUS_Period)))) - 1;