in the ./bench/verilog/i2c_slave_model.v
If an invalid slave address is issue, the state is still in idle state, so it keep shifting in the sda. Then a legal salve address maybe wrongly recognize and issue a write.
for this example code, 8'h22 is an invalid slave address, start, 8'h22, 8'h00, 8'h00, 8'h00, 8'h00, stop but this code will issue a write to memory 8'h20 with value 8'h20
I recommend to add a invalid_slave state, when an invalid slave address is issue, it enter to this state, and wait for a start/stop to go back to idle mode.