I2C controller core

In the tilte of ./bench/verilog/i2c_slave_model.v, there is a sentence

WISHBONE rev.B2 compliant synthesizable I2C Slave model

But it fail to compile using design compiler

The expression in the reset condition of the 'if' statement in this 'always' block can only be a simple identifier or its negation.

// generate statemachine
always @(negedge scl or posedge sto)
  if (sto || (sta && !d_sta) )
    begin
        state <= #1 idle; // reset statemachine

        sda_o <= #1 1'b1;
        ld    <= #1 1'b1;
    end
  else

The slave model is not synthesizable (anymore)