"With a 25MHz input clock and the prescale set to 0x31, I am seeing the I2C clock rate at 90.9KHz."
With that clock and prescale the core is being fed a 500kHz (2us) clock so it should be running at a nominal 100KHz (5 * 2us = 10us). Instead it looks to be running at 11us.
This may be due to the recent logic that synchronises and filters SCL, and then stalls the main clock until the filtered SCL rises. The logic is probably seeing these filtering delays as false "clock stretches" and as a result instead of generating a 4us/6us SCL clock train it is generating a 4.5us/6us train.
People using different clock sources with different dividers may get slower or faster resulting data rates.
It should be possible to handle clock stretch without stretching all clocks. It would be difficult with the existing design to handle this and still always obey the minimum SCL high time though.
I meant a 5us/6us SCL clock sequence.