OpenCores
Issue List
Clock prescaler #45
Open jgiampiccolo opened this issue over 4 years ago
jgiampiccolo commented over 4 years ago

Hi Richard,

Due to the addition of input filtering in module i2c_master_bit_ctrl.v in SVN rev. 74, the prescale formula in documentation (§3.2) is not valid anymore. In my case for example, system clock is 125MHz, prescale is 62 leading to a theoretical SCL frequency of 397kHz but the result is "only" ~355kHz.

Could you update the documentation? Thanks, Johan

rherveille commented over 4 years ago

I don't like the input filtering. I added it because some users requested it, but I don't think it is required. If I find some time I will review the code again.

Richard

raschutz commented over 2 years ago

Hi Richard,

Do you have an example of a top level VHDL file to connect the i2c core to Altera's Avalon bus?

Thanks, Robert Schutz.


Assignee
No one
Labels
Request