Issue List
Compile Errors with Quartus 15.1 #49
Open salmansheikh opened this issue about 6 years ago
salmansheikh commented about 6 years ago

I tried connecting this I2C core to the NEO430 with a WB bus but I keep getting errors with the unsigned (15 downto 0) so I am attempting to change all unsigned to std_logic_vector. Why would Quartus not give errors on this type?

connorspencer commented about 6 years ago

I am having the same issue. If you have found a solution I would love to know.

XXRyanXXL commented about 2 months ago

Same issue, using the VHDL RTL code. Just compile the verilog version and port map the signals of the verilog in a top level vhdl module.

No one