I2S to Parallel Interface

Hi OpenCores,

I was using this I2S_to-Parallel vhdl entity for my I2S core.

There is a somw problem in this as listed below -

1. The Counter goes down to 0 in the same cycle as LR_CK value changes. Being in an els if condition it is not able to detect the counter == 0 condition and hence not showing any data on output.

2. The shift register is not able to shift data for the entire data-width. A cycle is getting wasted when the shift register is reset to '0. This seems incorrect since we can't waste any cycle in the I2S protocol.

Thanks OpenCores.

1. You are right. I developed it keeping in mind the output of TI DIR9001 receiver (see the waveform: http://www.primianotucci.com/pub/i2s.jpg). It seem to be unlikely to happen in real-word situations since the bit_ck should exactly match the fs / (2 * bits ). Anyway it is conceptually wrong and should be fixed.

2. I do not agree. The first cycle was intentionally wasted since, according to the above waveform, the first data bit (MSB) is sent 1 cycle after the LRCK is toggled.

I hope to find time in this week end to fix it. Thanks a lot for your suggentions.

Primiano Tucci

Sorry, I misspelled the waveform URL (the parenthesis got caught in it).

The right url is: http://www.primianotucci.com/pub/i2s.jpg

Thanks for your reply.

Regarding issue 2 : you are right that the MSB should go one cycle later than LR_CK. But my concern was this,

--- the shift register that we are using in receiver has to shift for entire data width. --- What is happening is that when LR_CK changes, at that point the shift register is set to zero. Instead, it should have taken the LSB of the last data in this cycle. And from the next cycle, start shifting the next data, starting from the next data's MSB. --- I am saying that we shouldn't have any clock cycle in the stste-machine that sets that shift-register to '0 . Because than, we would be wasting one clock cycle.

Reply if there is still any doubt in the issue.

Thanks again.

Just found the reason for the issue -

--- In the waveform that you based your design upon, the data ends between one LR_CK value. You also have to consider the case, when the data width is same as width of LR_CK transition. That is the Transmitter is transmitting for the entire LR_CK value.

--- You can use the diagram mentioned on the first page of this I2S specs. www.nxp.com/acrobat_download2/various/I2SBUS.pdf