JPEG Hardware Compressor

Good afternoon,

I used the JPEG Hardware Compressor and tested it thanks to the Xilinx ISE Project navigator. It was running well with a Virtex 2 XC2V1000-4 but it used more hardware resources than you announced and it can't be implemented in the XC2V1000-4. I tried with a XC2V1500-4 and it was OK.

I don't know why there is those differences of compilation between your work and mine, have you got some ideas about that? What compiler did you use for your test?

I Thank you in advance.

Julien Morel Polytech'Orléans

I used Synplicity Synplify 7.6 and those were the hardware resources it used. It ran on the FPGA with several other cores.

LUT count with full optimization in synthesys was at 40%, as stated in here, so I can't understand why it can't fit in yours, as to use Xilinx for synth. would account only for a small increase in resource usage.

It'd be better if you explained which HW resources are you talking about, as I suspect that your problem is memory resources because maybe you've tried to synthesize a final image buffer larger than possible for the BlockRAM count of the FPGA.

Anyways with the resolution soft-limit of the core and its compression ratios, it shouldn't be necessary to have a buffer bigger than 60 KB (but it could overflow on very rare occasions) for the final jpg file.

If you've changed the code in order to compress images larger than CIF resolution or changed the compression ratios, then you would need another FPGA (with more BlockRAM) or change the code to make it save the final image in an external memory.

Regards,

Víctor López

Finally i could able to manage to simulate the Hardware Compressor code , strange thing is am getting an output "image.jpg" but the content is missing i.e a plain image ....i have tried and analyzed but couldn't trace the problem....

can you see and suggest me ...