JPEG Hardware Compressor

I have a final project as same as your JPEG Hardware Compressor. Basically, I'm doing the same, JPEG image compression in actual hardware by using FPGA (NEXYS3) as a hardware, and XILINX as a software. I need a code that can be synthzisable and it can generate a bitstream that can be downloaded into the FPGA. I saw you caode in the download but they are not 9 vhdl file as you mentioned i Can you plz help me with this?