Hi,

First of all thanks for sharing the codes.

I'm trying to run a simulation using the test bench, i.e. outputEncoder_tb. However, there are various errors and it exists the simulation. I'm using Modelsim 10.1c and I got this error message:

** Error: (vsim-86) Arg Value -1 is out of NATURAL range 0 to 2147483647.

Time: 0 ps Iteration: 0 Instance: /outputencoder_tb/DUT

** Error: (vsim-86) Arg Value -1 is out of NATURAL range 0 to 2147483647.

Time: 60 ns Iteration: 1 Instance: /outputencoder_tb/DUT

** Fatal: (vsim-3421) Value -1 is out of range 0 to 16.

Time: 60 ns Iteration: 1 Process: /outputencoder_tb/DUT/suppressCntPrcs File: ../verilog/outputEncoder.vhd

Fatal error in Process suppressCntPrcs at ../verilog/outputEncoder.vhd line 122

HDL call sequence:

Stopped at ../verilog/outputEncoder.vhd 122 Process suppressCntPrcs

Have you seen this before? Would you mind to tell me what simulator are you using?

Thank you very much. Your help is greatly appreciated.

Best regards, Boon