MADI Receiver

Hi, I plan on using an ethernet phy to implement a propietary 100mbs fiber-link for an embedded system. I think you code would be a great place to start to get a grasp at the mii interface etc. The ports for the madi_to_adat component is different in the testbench than in the madi_receiver.vhd file.

from madi_testbench.vhd: component madi_to_adat port( clk_125_in : in std_logic; madi_in : in std_logic; -- missing in madi_receiver.vhd

word_clk_in : in std_logic; -- missing in madi_receiver.vhd -- word_clk_out : out std_logic; bit_clk_in : in std_logic; adat_0_out : out std_logic; adat_1_out : out std_logic; adat_2_out : out std_logic; adat_3_out : out std_logic; adat_4_out : out std_logic; adat_5_out : out std_logic; adat_6_out : out std_logic; adat_7_out : out std_logic ); end component;

from madi_receiver.vhd: entity madi_to_adat is port( madi_clk_in : in std_logic; -- missing in madi_testbench.vhd madi_data_valid : in std_logic; -- missing in madi_testbench.vhd madi_symbol_in : in std_logic_vector(4 downto 0); -- missing in madi_testbench.vhd clk_125_in : in std_logic; word_clk_out : out std_logic; -- commented out in madi_testbench.vhd bit_clk_in : in std_logic; adat_0_out : out std_logic; adat_1_out : out std_logic; adat_2_out : out std_logic; adat_3_out : out std_logic; adat_4_out : out std_logic; adat_5_out : out std_logic; adat_6_out : out std_logic; adat_7_out : out std_logic ); end madi_to_adat;

My guess is that your code may work perfectly fine but the testbench is outdated. Do you have an updated version of the testbench to help me getting started?

reagards, Øyvin Eikeland

I agree. I'm looking into it...

Chris