Manchester to UART converter

Hi,

I'm new to VHDL, so I could be off track here, but when I see: signal clock_timer : std_logic_vector(5 downto 0); followed by: if clock_timer /= 108 then

alarm bells start ringing, because 108 (16#6C#) requires 7 bits, not 6. I can't believe that this is really what is happening, since otherwise the else clause where the real business is happening would never be executed.

Regards,

Julian

Thank you for your reporting. That bug already fixed but no update here, sorry.

Please change 108(b1101100) to 44 (b101100).

The "clock_timer" just get from mcu's clock and to gen slower clock "timer". the MSB of 108 is not in use.