MB-Lite

Looking at the mblite, it seems that there is no way to stall the processor to wait for data on the IMEM bus. This would be advantageous since it allows a few additional options in interfacing with instruction memory:

1) Allow use with slow memory or memories with different speeds 2) Allow use with bursty memories (like a cache) 3) Allow for the DATA and MEM to occupy the same memory and/or share a bus

While this doesn't help the performance at all, it certainly would seem to make the core more flexible, and allow mblite to more closely mirror the MicroBlaze architecture.

Has any thought gone into implementing something along these lines?

You could use the enable line of the data memory interface to stall the processor. I don't see the advantage of separate lines for these functionalities, because I think that this would would be the same as an OR operation on the enable and stall signals and hence does not belong to the functionality of the core.

This method is also used by the wishbone bus component to halt the processor when more than one clock cycles are used for a transfer. You can probably use this component as a reference for your design.

Furthermore, the multiplexed bus component enables you to split the dmem interface into multiple smaller interfaces - the enable signal of the dmem interface is also OR'ed in this case with all enable signals of the sub-interfaces.