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Register outputs in bin2vhd_4x8b.c #8
Closed Rythan opened this issue over 13 years ago
Rythan commented over 13 years ago

Hi, I've spent a while getting MB-Lite to compile under the Xilinx tools. I found that the trick of using 4 x 8 bit memories for dmem was necessary to prevent weird ISE synthesis crashes. I discovered a bug in bin2vhd_4x8b.c while generating these memories: do0 - do3 are asynchronous in the generated VHDL, and should be moved inside the process(clk_i) section, as they are in bin2vhd_32b.c. After I found this, simulation and synthesis were all correct. Thanks for a useful project!

takar commented over 13 years ago

Thanx for the report! I will fix this bug ASAP.

takar commented over 13 years ago

Thanks for your patience. I have just committed the updated version. Besides the weird crashes in some versions of ISE, it also turned out that in my own version the generated VHDL didn't create Block RAM but distributed RAM instead.

takar closed this over 13 years ago
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