Mini-Risc core

Dear all,

When I tried to do synthesis, it fails.

The following files are missing. They should be located out of the project directory priginally by the designer. These files are also called in "\minirisc\trunk\sim\run" for simulation in NC-Verilog.

	../../generic_memories/rtl/verilog/generic_spram.v	\
	../../generic_memories/rtl/verilog/generic_dpram.v

In "\minirisc\trunk\verilog\core\register_file.v" (line 109),

generic_dpram #(7,8) rf0( .rclk( clk ), .rrst( rst ), .rce( 1'b1 ), .oe( 1'b1 ), .raddr( rd_addr ), .do( rf_rd_data_mem ), .wclk( clk ), .wrst( rst ), .wce( 1'b1 ), .we( rf_we ), .waddr( wr_addr ), .di( rf_wr_data ) );

In "\minirisc\trunk\verilog\core\risc_core_top.v" (line 175),

generic_spram #(11,12) imem( .clk( clk ), .rst( rst_in ), .ce( 1'b1 ), .we( 1'b0 ), .oe( 1'b1 ), .addr( inst_addr ), .di( 12'h0 ), .do( inst_data ) );

Regards,

Patrick

These memories are not part of the MiniRisk project.

yes, missing generic_dpram.v and generic_spram, weijie11@126.com