MIPS32 Release 1

When the following code is executed, it seems to ignore the JALR insn. On the simulator (iSim), it appeared to stall on the insn at 5c0, at the same time it is loading the value into register v0, no doubt because it's waiting for v0 to become valid. The stall lasts for two memory cycles (fetches the 5c0 insn three times), then executes the J insn at 5c4:

 5b0:       02112023        subu    a0,s0,s1
 5b4:       8c420000        lw      v0,0(v0)
 5b8:       00042083        sra     a0,a0,0x2
 5bc:       0040f809        jalr    v0
 5c0:       02202821        move    a1,s1
 5c4:       08000178        j       5e0 <CommandLoop+0x1e4>
 5c8:       3c040000        lui     a0,0x0

Sorry I can't provide more info than that. I can't easily ship you any code. I am using your standalone CPU with both the I & D buses connected to a dual port RAM crafted from the Xilinx block RAM, running on a Spartan-6.

Your CPU seems well written, and fairly solid, other than this problem. It was easy to drop into my project, taking only an hour or two. Thanks!!!

Neil.

Hi Neil, thanks for submitting the bug.

Issue

Jalr does not jump to the correct address.

Cause

The ID Rs forwarding mux doubles as a link address selector for the Bal and Jal type instructions. These two functions are mutually exclusive for all instructions except Jal, which both links and reads a register from the forwarding system. The selection between address injection and register reads must be decoupled.

Solution

Link address injection has been moved to the EX stage, and the ID Rs forwarding mux now only supplies register reads. This change incurs no performance penalty or additional hardware cost, and is detailed below.

1. Disconnect input 3 from IDRS Fwd Mux.
2. Place EX RestartPC as input 3 to EXRS Fwd Mux.
3. Change input 3 of EXRT Fwd Mux to '8' instead of '4'.

The restart PC is always the PC of the same instruction, unless the instruction is in a branch delay slot. Since branches and jumps are not allowed in delay slots, the restart PC is appropriate for use in link address computation.

Modified Files

1. Processor block diagram
2. Processor.v
3. Hazard_Detection.v

<i>These two functions are mutually exclusive for all instructions except Jal<b>r</b>...</i>