JPEG Encoder

Hi,

I've recently tested this project on a Kintex 7 -2 FPGA with VVD 2015.4.

It runs correctly and generated good jpeg image. The fmax is ~180MHz.

When I tried to improve fmax, I found that critical path is U_ROMR/datao to multiplier input, which is not registered at all. I tried to reg "romr_datao" and "a" and fmax improved to ~210MHz.

Don't forget to change U_quantizer/pipeline_reg width from 5 to 6, cause r_divider add a stage of pipeline.