signal "memswitchwr_s" in mdct.vhd needs to be delayed by two cycles, otherwise the last two outputs of DCT1D are written to the wrong memory because "memswitchwr_s" switches to early.
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bug caused corruption of the last row of each 8x8 DCT, only visible at high quality compression (I used 100%) and if high frequency content (e.g. sharp lines) is present in the image.
Hi Stephan,
Thanks for finding it. I will run simulation to observe it.
Michal
bug caused corruption of the last row of each 8x8 DCT, only visible at high quality compression (I used 100%) and if high frequency content (e.g. sharp lines) is present in the image.
Stephan,
I corrected the sources.
Thanks Michal