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mdct - memory switching #8
Open sberner3 opened this issue about 12 years ago
sberner3 commented about 12 years ago

signal "memswitchwr_s" in mdct.vhd needs to be delayed by two cycles, otherwise the last two outputs of DCT1D are written to the wrong memory because "memswitchwr_s" switches to early.

sberner3 commented about 12 years ago

Type your text here

sberner3 commented about 12 years ago

bug caused corruption of the last row of each 8x8 DCT, only visible at high quality compression (I used 100%) and if high frequency content (e.g. sharp lines) is present in the image.

mikel262 commented about 12 years ago

Hi Stephan,

Thanks for finding it. I will run simulation to observe it.

Michal

sberner3 commented about 12 years ago

bug caused corruption of the last row of each 8x8 DCT, only visible at high quality compression (I used 100%) and if high frequency content (e.g. sharp lines) is present in the image.

mikel262 commented about 12 years ago

Stephan,

I corrected the sources.

Thanks Michal


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