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Simulation fails after reset #2
Closed ldingle opened this issue over 10 years ago
ldingle commented over 10 years ago

I tried a simulation with Aldec's Active-HDL v9.3. If I assert and de-assert RESET, the simulation hangs with M1 & MEMRQ asserted and ADDR="xxxx". Without RESET it seems to run normally. Any suggestions?

ndumitrache commented over 10 years ago

Probably playing with the simulator settings will give you an insight. The simulation with XILINX ISE ISIM simulator, as the real FPGA implementation, have no this problem.

ndumitrache closed this over 10 years ago

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