OpenRISC 1000

OpenRISC architecture manual:

p.254: "Instruction fetch virtual EA" for I-TLB miss, I-PF and illegal instruction exceptions should be clarified as been the PC of the instruction (following or1200_except.v)

p.254: Maybe nothing can be done now, but trap, syscall and D-TLB miss share a priority of 7, and tick timer and external interrupt share priority 12 (this last is somewhat more understandable), so it ends up being the implementor's choice if two of these exceptions happen at the same time (veeery rare).

p.62 and p.63: For l.jal and l.jalr the link register is not specified, implementors may think it is a SPR, but only in the ABI section LR is listed as R9 (p.334). I think it should be explicitly said.

p.119: In the l.sub implementation the carry flag is set, but in the description it explicitly says (with an orthographical error here in upper case): "The ISNTRUCTION does not change carry SRCY flag.". From the verilog source of OR1200 I think it is not changed indeed, so 32 and 64 bit implementation in that page are wrong. Check it, please.

p.28: very minor: in the description of EPH it says: "0 Exceptions vectors ..." and "1 Exception vectors...", in 0 it should "exception vectors" without the s.

• For arithmetic operations, the difference between carry and overflow should be explicitly stated, as carry applies to unsigned operands and overflow to signed ones, but the operations do not distinguish operands. In a 32 bit addition, to me, overflow occurs in: sum33(32 downto 0) <= (a(31) & a(31 downto 0)) + (b(31) & b(31 downto 0)) when sum33(32)/=sum33(31) and carry is just sum33(32). Please, correct me if mistaken.

Regards,

Victor Lopez Design Engineer VISENGI - www.visengi.com