Parallel CRC Generator

Hi guys!

This tool comes in really handy. Especially if you have a weird non-standard polynome and don't know where to start. But...

I had a weird non-standard polynome and decided to use this tool. Simulating the code in Xilinx ISE: Works OK!. Simulating in Aldec Simulator: OK!. Synthesize it and load it on a NB3000 to test: Failed!.

I'll report what I found, if this is somehow my fault.

Hi,

Sounds like a simulation/synthesis mismatch. Can happen for lots of reasons, such as optimization during synthesis or physical implementation.

Can you please provide more details on what exactly failed. Also, can you please upload synthesis and implementation reports (is it Xilinx FPGA ?). Also, if possible the source code that instantiates the core.

Thanks, Evgeni