Parallel CRC Generator

When generating a VHDL crc encoder, some of the lines have Verilog comment characters. It's easy to correct this manually, but it would be nice if is correct from the start.

I run Windows 7 64-bit, and I used the following command line: crc-gen\crc-gen vhdl 8 16 1021 > csi2_crc.vhd

The result is the following:

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// CRC module for // data(7:0) // crc(15:0)=1+x^5+x^12+x^16; // library ieee;
use ieee.std_logic_1164.all;

entity crc is port ( data_in : in std_logic_vector (7 downto 0); crc_en , rst, clk : in std_logic; crc_out : out std_logic_vector (15 downto 0)); end crc;

architecture imp_crc of crc is signal lfsr_q: std_logic_vector (15 downto 0); signal lfsr_c: std_logic_vector (15 downto 0); begin
crc_out <= lfsr_q;

lfsr_c(0) <= lfsr_q(8) xor lfsr_q(12) xor data_in(0) xor data_in(4);
lfsr_c(1) <= lfsr_q(9) xor lfsr_q(13) xor data_in(1) xor data_in(5);
lfsr_c(2) <= lfsr_q(10) xor lfsr_q(14) xor data_in(2) xor data_in(6);
lfsr_c(3) <= lfsr_q(11) xor lfsr_q(15) xor data_in(3) xor data_in(7);
lfsr_c(4) <= lfsr_q(12) xor data_in(4);
lfsr_c(5) <= lfsr_q(8) xor lfsr_q(12) xor lfsr_q(13) xor data_in(0) xor data_in(4) xor data_in(5);
lfsr_c(6) <= lfsr_q(9) xor lfsr_q(13) xor lfsr_q(14) xor data_in(1) xor data_in(5) xor data_in(6);
lfsr_c(7) <= lfsr_q(10) xor lfsr_q(14) xor lfsr_q(15) xor data_in(2) xor data_in(6) xor data_in(7);
lfsr_c(8) <= lfsr_q(0) xor lfsr_q(11) xor lfsr_q(15) xor data_in(3) xor data_in(7);
lfsr_c(9) <= lfsr_q(1) xor lfsr_q(12) xor data_in(4);
lfsr_c(10) <= lfsr_q(2) xor lfsr_q(13) xor data_in(5);
lfsr_c(11) <= lfsr_q(3) xor lfsr_q(14) xor data_in(6);
lfsr_c(12) <= lfsr_q(4) xor lfsr_q(8) xor lfsr_q(12) xor lfsr_q(15) xor data_in(0) xor data_in(4) xor data_in(7);
lfsr_c(13) <= lfsr_q(5) xor lfsr_q(9) xor lfsr_q(13) xor data_in(1) xor data_in(5);
lfsr_c(14) <= lfsr_q(6) xor lfsr_q(10) xor lfsr_q(14) xor data_in(2) xor data_in(6);
lfsr_c(15) <= lfsr_q(7) xor lfsr_q(11) xor lfsr_q(15) xor data_in(3) xor data_in(7);

process (clk,rst) begin if (rst = '1') then lfsr_q <= b"1111111111111111"; elsif (clk'EVENT and clk = '1') then if (crc_en = '1') then lfsr_q <= lfsr_c; end if; end if;
end process; end architecture imp_crc;