PID controller

I made modifications to improve the design and fix bugs.

• First problem I noticed is the update_kpd & update_esu signals which are high only when the inputs pv or sp were just updated. At that moment, the PID can be calculating a new output for instance, when he finishes, signals update_kpd or update_esu are low and won't be recalculated while the inputs have been updated.

• I would also request comments in the source code. It is difficult to understand the code despite the good documentation without comments explaining what is done and why.

• It is stated that the PID calculates an output in 17 cycles. In fact, it will calculate a new kpd parameter and a new output in 18 cycles. If Kp or Kd have not been updated, an output can be calculated in 14 cycles

• Finally, the pipeline can be improved to reduce the calculation time (note that the pipeline described in the documentation doesn't correspond to the one originally implemented in Verilog). I could reduce Kpd+U(n) calculation to 15 cycles, U(n) calculation to U(n) only to 11 clock cycles. See my pipeline design here: http://i49.tinypic.com/2113pcw.jpg

I will try to upload my code soon, but i removed the WishBone interface!

Regards,

J-B

The first problem is solved by write lock bits wl0:7. When calculation of Kpd or un is in progress the relevant write lock bits for all operands are high, this will stall the update to Kpd or PV or any other operands in use until the calculation finishes. So during that period the update_x will never be high.

I have put a block diagram into the user manual to show important signals and their connections. I will write more comments soon.

Your idea of reducing the calculation time is very good. I just update a new PID.v that also reduces the calculation time. And it will be more shorter if your idea is added in.

I will try to use your idea to improve the code. And I am looking foreword to your codes.

Regards,

Todd