PLBv46 to Wishbone Bridge

There are various omissions and errors in the plbv46_2_wb.pdf document.

1) There is no specific reference to the granularity or operand size for the bridge. This is required to be defined per Wishbone Specification Rule 2.15. It would seem that the granularity is 8-bits based upon the number of select lines, but confirmation would be useful. Technically the port size should be more clearly stated as well, but the document does state the core has a 32-bit interface.

2) Some block diagram should be included.

3) Some information on the actual operation of the bridge should be included.

4) The information in the clocking section is incorrect. There is no clk_pad_i port referenced in the source HDL. There is no wb_clk_I referenced in the source HDL, instead the clock and reset are obtained from the PLB side of the bridge, which means that this core is effectively both a Wishbone master and the SYSCON block which is not indicated in the document. There is no sm_clk_i port.

5) The I/O ports section does not list all of the Wishbone ports used and includes a reference to "foo_pad_o" which is not in the source HDL at all.

6) There is no information on whether this bridge is big endian, little-endian, or both.

2) Added some block diagrams to demonstrate how to connect up cores to the system.

4) Fixed the clocking information.

5) Fixed the IO Ports section.

Will be fixing the other items shortly.