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Open ocghost opened this issue almost 19 years ago
ocghost commented almost 19 years ago

I'm synthesize top.v in ps2_soc2.zip found error Compiling include file "../top.v" ERROR:HDLCompilers:26 - ../top.v line 236 expecting '}', found ',' ERROR:HDLCompilers:26 - ../top.v line 236 expecting ';', found ':' ERROR:HDLCompilers:26 - ../top.v line 236 expecting 'end', found '0' ERROR:HDLCompilers:26 - ../top.v line 236 expecting 'end', found ';' ERROR:HDLCompilers:26 - ../top.v line 237 unexpected token: '<=' ERROR:HDLCompilers:26 - ../top.v line 237 unexpected token: '-' ERROR:HDLCompilers:26 - ../top.v line 237 unexpected token: '[' ERROR:HDLCompilers:26 - ../top.v line 237 unexpected token: '[' Module <top> compiled Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"


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