SHA cores

Hello!

Thanks for a useful initiative!

I tried to compile the sha256 and test with iverlog (version 0.9.3)

I did this

mymachine> iverilog rtl/sha256.v bench/test_sha256.v mymachine> ?./a.out ERROR(SHA-256-00) Expected 248d6a61, Got 00000000 ERROR(SHA-256-01) Expected d20638b8, Got 00000000 ERROR(SHA-256-02) Expected e5c02693, Got 00000000 ERROR(SHA-256-03) Expected 0c3e6039, Got 00000000 ERROR(SHA-256-04) Expected a33ce459, Got 00000000 ERROR(SHA-256-05) Expected 64ff2167, Got 00000000 ERROR(SHA-256-06) Expected f6ecedd4, Got 00000000 ERROR(SHA-256-07) Expected 19db06c1, Got 00000000

I also added some dumpfile entry to the test_sha256.v and it seems that there is never any vectors output. The A-H registers contain data but I cannot seem to find anything that looks like the test vectors expected values.

In test_sha256.v add an extra clock after deasserting clk_w_i before comparing text_o values. The core is doing the right thing, the testbench needs to be updated though.

@(posedge clk);
cmd_w_i = 1'b0;

@(posedge clk);

for (i=0;i<8;i=i+1)

Please disregard above comment, as it applies to the other bug.