I recently began experimenting with this SPI core. In our application, I felt that having a slave select generated by the state machine instead of cpu controlled would help improve overall performance of the SPI interface. I also added a register outside of the SPI core to be able to override the state machine generated slave select. That would provide the option of holding slave select active between byte transfers. I can make my modification available in case you would be interested in adding it to the design you have provided here.
I was actually thinking of 8 data registers. Writing/reading to one of these registers would then enable the associated CSn. So up to 8 slaves could be connected.
What do you think?
Type your text here I'm afraid that I don't understand the value in using eight data registers for selecting individual CSn generation.
The modification that I started so far only deals with a single CSn. I could envision expanding on it to allow for multiple CSn by creating a bit field in a new slave select register (or Extensions reg?). Then that slave select register could be written to just prior to writing to the Data reg when transmitting. Decode of the bit field would turn on the selected slave as the state machine controls its common slave select control.