Single Clock Unsigned Division Algorithm

I have tried to synthesize the the project, which contains a single RTL module (div_unit.vhd). I use Xilinx ISE 12.1 and the integrated synthesizer XST.

I get this :

ERROR:HDLParsers:3014 - "E:/XilinxDesigns/one_clock_cycle_divider/div_unit.vhd" Line 30. Library unit definitions is not available in library work.

Line 30 is: use definitions.all;

As I am a verilog user, I don't know if I have done something wrong with the VHDL project, or if something is really missing from the project. Can you advise ? Thanks,

Tullio