Storm Core (ARM7 compatible)
multi cycle memory access #2
Closed zero_gravity opened this issue over 13 years ago
zero_gravity commented over 13 years ago
When performin multi cycle memory access operations, the pipeline halt/enable doesnt work properly and only the first cycle is executed.
Example: Write Rx to the memory and add to the address register Ry an offset afterwards
=> only the memory write is executed
zero_gravity closed this over 13 years ago
© copyright 1999-2018 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.