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Storm Core (ARM7 compatible)

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multi cycle memory access #2
Closed zero_gravity opened this issue over 13 years ago
zero_gravity commented over 13 years ago

When performin multi cycle memory access operations, the pipeline halt/enable doesnt work properly and only the first cycle is executed.

Example: Write Rx to the memory and add to the address register Ry an offset afterwards

=> only the memory write is executed

zero_gravity closed this over 13 years ago

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