synchronous_reset_fifo with testbench

The signals under reset are assigned with tightly coupled value and are not related to PARAMETERS. What's going on if PARAMETER WIDTH is set to 16 ? You are lucky because it is permissive verilog... in VHDL you will be fired!!!

if (resetn == 1'b0) begin

    write_ptr <= 5'b00000;
    read_ptr <= 5'b00000;
    data_out <= 8'b00000000;

That's the same problem with the way you assign your flags.

assign empty = ((write_ptr - read_ptr)== 5'b00000) ? 1'b1 : 1'b0; assign full = ((write_ptr - read_ptr) == 5'b10000) ? 1'b1 : 1'b0;

I've modified your code to make it working for me with cascaded parameters. Here it is. Feel free to integrate it or not. It is under user responsibility to control flags so I've removed your checks and added a difference counter. I have verified it on my side (not using your TB) and it is working perfectly for me.

//Fifo Module
module fifo(clock,write_enb,read_enb,data_in,data_out,empty,full,resetn);

parameter WIDTH = 8;
//parameter DEPTH = 16;
parameter POINTER_SIZE = 5;

localparam DEPTH = (1 << POINTER_SIZE);

//Inputs
input clock;
input resetn;
input write_enb;
input read_enb;
input [WIDTH-1:0] data_in;

//Outputs
output [WIDTH-1:0] data_out;
output empty;
output full;

//Wires and Internal Registers
wire empty;
wire full;
reg [WIDTH-1:0] memory [0:DEPTH-1];
reg [POINTER_SIZE-1:0] write_ptr;
reg [POINTER_SIZE-1:0] read_ptr;
reg [POINTER_SIZE:0] diff_ptr;
reg [WIDTH-1:0] data_out;


//Asynchronous Logic
//FIFO full and empty logic

//assign empty = ((write_ptr - read_ptr) == 5'b00000) ? 1'b1 : 1'b0;
//assign full  = ((write_ptr - read_ptr) == 5'b10000) ? 1'b1 : 1'b0;

assign empty = (diff_ptr == 0) ? 1'b1 : 1'b0;
assign full  = (diff_ptr == DEPTH-1) ? 1'b1 : 1'b0;

//Synchronous Logic
//FIFO write and read logic
always@(posedge clock)
begin
   if (resetn == 1'b0)
     begin
        write_ptr <= 0;
        read_ptr  <= 0;
        diff_ptr  <= 0;
        data_out  <= 0;
     end
   else
     //Simultaneous Read and Write
     begin
        if (write_enb == 1'b1)
          begin
             memory[write_ptr] <= data_in;
             write_ptr <= write_ptr + 1;
          end
	if (read_enb == 1'b1)
          begin
             data_out <= memory[read_ptr];
             read_ptr <= read_ptr + 1;
          end
	// diff count
        if ((write_enb == 1'b1) && (read_enb == 1'b0))
	  diff_ptr <= diff_ptr + 1;
        else if ((write_enb == 1'b0) && (read_enb == 1'b1))
	  diff_ptr <= diff_ptr - 1;
     end
end
endmodule