T51 mcu

If I get the Wishbone specs right, during a write-cycle, Strobe, Cycle and Write Enable should be asserted (see 3.2.2. SINGLE WRITE cycle). This is not the case when I instantiate the core without any internal XRAM by setting XRAMAddressWidth to zero.

The external Wishbone signals are defined like this: XRAM_CYC_O <= ext_ram_en and ram_access; XRAM_STB_O <= ext_ram_en and ram_access; XRAM_WE_O <= RAM_Wr;

Tracing ext_ram_en to its driver: zeros <= (others => '0'); g_rams0 : if XRAMAddressWidth > 15 generate ext_ram_en <= '0'; -- no external XRAM end generate;

g_rams1 : if XRAMAddressWidth < 16 and  XRAMAddressWidth > 0 generate -- >= ??
	ext_ram_en <= '1' when XRAM_Addr(15 downto XRAMAddressWidth) /= zeros else 
	              '0';
end generate;

One can see that when XRAM_AddressWidth is zero, ext_ram_en is never driven high. The fix is already in the code above, in form of a comment. So the line in question should be:

g_rams1 : if XRAMAddressWidth < 16 and  XRAMAddressWidth > =0 generate

While looking at the code, I wondered if XRAM_WE_O should also be qualified with ext_ram_en (and probably ram_access?) like so XRAM_WE_O <= ext_ram_en and RAM_Wr;