Define Inputs and Outputs.
Top Level should not contain logic statements. If it is necessary, a new submodule should be created.
As of today (March 6th) some of the I/Os have been defined and commited. The idea is that the ALU will be as small as possible therefore it will not deal with the macro-ops. Instead it will be receiving control signals from the FSM, i.e. add, sub, cmp, etc. However, these signals were not create yet.